Update on FADC/CFD System

Since the original VERITAS proposal was submitted, the design of the VERITAS FADC board has been completed. Printed circuit board (PCB) fabrication and gate-array programming are complete, stuffing and testing of the first 10 channel boards are now in progress. The FADC data acquisition scheme has been revised, and now includes reflective memory to merge data and provide a high-speed interconnection between crates. We have analyzed data taken with the prototype one-channel FADC system, and have used simulations to more rigorously justify the use of a 500 mega-sample per second (Msps) digitization rate. We have also developed a detailed plan for the complete fabrication of the boards by sub-contractors, and for the testing and maintenance of the boards throughout the construction phase of the project. The main points covered are summarized below:

• The FADC system for one telescope now consists of 51 10-channel 9U VME boards, with 17 located in each of 3 crates. High power Wiener crates with CERN v430 backplane will be used. A clock/trigger board in each crate will provide synchronous clear, trigger, and 500MHz clock signals over a custom J3 backplane. This board will also latch the universal event number received by the DOT and presented on the ECL header. The J3 backplane will also supply busses for additional power.

• The FADC board serves as a motherboard for the Constant Fraction Discriminators (CFDs), providing DACs for threshold control, a singles rate scaler, buffering of the hit pattern programmable trigger delay and VME interface. The CFD design effort has been decoupled by putting the discriminator circuit on a mezzanine board with SIP connector pin-outs compatible with existing commercial CAEN CFD boards. This will allow alternate schemes for the discriminator to be explored.

• The total cost per channel for the finished, tested FADC/CFD boards will be <$585 including the current CFD design.

• Each crate will contain a CPU and reflective memory module for readout control, event building and buffering.

• The FADCs will use the D32 Chained Block Transfer (CBLT) to efficiently transfer variable length data distributed among the 17 modules over the VME bus.

• FADC boards include a local SRAM (one on each 10-channel board) which is capable of on-board buffering of event data (initiated by the trigger signal) before data is read by the VME CPU over the backplane.

• The closest viable commercial device, the Acquiris Model DC265 CompactPCI/PXI 500MHz FADC, is more than twice as expensive as the combined FADC/CFD board (the quote for VERITAS is $\sim$$1250 per channel), has a much lower channel density (4 per board, 8 boards per PCI backplane) requiring many more CPUs, no ability to extend the dynamic range above 8 bits, no ability to latch the CFD hit pattern, and lacks the ability to chain data transfers, resulting in a much larger read-out dead time.

• Simulations indicate an improvement in the signal to noise ratio and charge reconstruction quality factor of at least 11% in going from 250 Msps to 500 Msps. However, this requires significant real time processing to perform a sinc function interpolation. Without this processing, the difference is even larger, $\sim$34%.

• Tests of the one-channel FADC board on Whipple indicate an improvement in the signal to noise ratio (for image reconstruction) of $\sim\,\sqrt{2}$ compared with the existing GRANITE-III electronics based on measurements of light pulser signals (signal) and pedestal variances (noise).

• The FADC board also stores the CFD state for every 4 samples in the same channel ring buffer used to store the FADC data. This provides a record of the triggering pixel hit pattern for every triggering event up to any trigger rate at which the telescope can be operated (e.g., a 1MHz telescope trigger rate).

• Use of a hardware CFD trigger provides a low time jitter gate which is required to produce an optimal charge measurement for on-board zero-suppression and to minimize the data window (and hence the data rate).