FADCs

The high speed flash encoder system will provide a dramatic increase in the information available, and will no doubt be a powerful tool in reducing the energy threshold and raising the general performance of the experiment. The proposed system is clearly the ``technology frontier'' of the experiment. General concerns include:

a)

There didn't appear to be a frequency bandwidth consensus in the analog signal path chain from the preamplifier to the flash encoder input. The system stability will be improved by operating all the analog subsystems at the minimum required bandwidth.

b)

It wasn't clear what the required linearity relationship is between the pulse voltage, which fires the trigger discriminators, and the charge integral data provided by the flash encoder. Since the experiment endeavors to run at the lowest possible threshold, it's likely that this relationship will be relevant in understanding the low energy data.

c)

Simultaneous digitization and acquisition: A common problem of encoders that acquire and digitize simultaneously (buffered operation) is acquisition induced corruption of the digitization. The designers stated that buffered operation will be supported but is not required for successful operation of the system.

d)

Power consumption: The flash encoder system presents a large thermal load, and sufficient cooling AND cooling system interlocks are a MUST in a system like this.

e)

Schedule issues: The proposed system is largely based around very high speed multi-layer analog/digital printed circuit boards. The designers have allowed effectively two prototype iterations, which seems like an aggressive schedule for a board of this complexity. Fortunately the designers are working closely with the printed circuit board vendor, which has delivered prototype boards in a timely way.